how to efficiently drive async SRAM?

If you want access to the waitrequest signal, you will need to write your own component using HDL. Alternatively, using the component editor you can manually specify a fixed number of read and write wait states, which should be enough in your case.

You will probably still need to have at least one read state though. In addition to the SSRAM's 8ns, you have some I/O delays and routing delays inside the FPGA that can make the hole access time over one clock period. Some SRAMs can be used synchronously with pipelining and in this case you can more reliably have one read or write access per clock cycle, but you will have to write your own controller in HDL.