How to divide a clock by two without using a PLL?

Hello @sreekumar.regu.girijakumari​ ,

Yes, the clk_div2 register is adding alot of delay. About 8 ns. So I needed to add FIFO's to buffer between the MII clocks and RMII clock.

For the most part, Xilinx IP is incredibly cumbersome and poorly designed compared to Altera, but they have some nice features such as the BUFR. It occurred to me I might use the clk_div2 as an enable for the ALTCLKCTRL instead of the input. But in the end, it's probably best if I have enough PLL's and clock inputs to avoid the problem.