Forum Discussion
corestar
Contributor
ContributorHow to divide a clock by two without using a PLL?
I'm using the Altera Tri-Mode EMAC for 10/100 Ethernet with MII interface to the Phy. This uses 25 MHz tx_clk and rx_clk generated by the Phy and going to the EMAC. These clocks do NOT use dedicated ...
SreekumarR_G_Intel
Frequent Contributor
Frequent ContributorHello David ,
Sorry for the late reply ,
Actually I am trying to find is there any IP for FPGA for the clock division. I didn't find any sorry if i missed out too.
From the clk division RTL output connected ALTCLKCTRL IP which is looks me connected to the buffer, but still iam worried adding flop in between the clock will add more jitter or skew.
I never tried the way iam suggesting, But I didnt see any other way.
can you kindly let me know how i can help you further ?
Thank you ,
Regards,
Sree
