Jianing1
New Contributor
1 year agoHow to configure the dsp ip core to make a 16-bit 3-input adder with good timing
Hi, I want to use DSP to do the internet checksum offloading. I want to do a+b+c (16 bits) in one clock and I am using Agilex7 AGFB023R25A2E2V.
I selected Native Floating Point DSP and configured to "Sum of two FP16 multiplication with FP32 addition mode" using "fp16_mult_top_a*fp16_mult_top_b(16'b1) + fp16_mult_bot_a*fp16_mult_bot_b(16'b1) + fp32_adder_a".
However, the timing of my project changed from 0 ns to -2 ns with about 18 DSP enabled. Do you know how to configure the DSP to have a better timing performance? Do I have a better choice for the IP core?