How to call an IP designed in Verilog in Intel HLS compiler?

Is it possible to design and optimize an IP in Verilog and create a function for it that can be called from HLS?

A simple example of such scenario would be as follows:

1. Design and optimize an FIR filter in Verilog.
2. Create a function for the design in HLS.
3. Write a nested `for` loop in HLS that calls the function associated with the filter.