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Tozpen50's avatar
Tozpen50
Icon for New Contributor rankNew Contributor
7 years ago

How the data is transferred by TX port of Avalon-MM PCIe

Hi, We are developing a PCIe application with SGDMA DMA controller. The SGDMA mm_write port (128 bits wide) is connected to the slave TX port of Avalon-MM V PCIe core. The SGDMA 'Burst Enable' optio...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

​Hi,

Thank you for clarifying that you are using AVMM Cyclone V Hard IP. By referring to the user guide, the txs_burstcount, the count unit is the amount of data that is transferred in a single cycle, the width of the write/read data can be 64 or 128 bits. There is a txs_byteenable port, so the padding from the user logic is not required as i can see.

Regards -SK