Forum Discussion

corestar's avatar
corestar
Icon for Contributor rankContributor
2 years ago

How is PCIe coreclkout_hip generated?

I'm using a Cyclone V GT PCIe Avalon ST core. It might be helpful to use coreclkout_hip to run our application layer, but it is not clear how that clock is generated and how much jitter it has. I ha...
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Corestar,


Glad that my suggestion able to help you to move forward.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.


  • corestar's avatar
    corestar
    Icon for Contributor rankContributor
    2 years ago

    Hello,

    It's still not very clear how all this works, but apparently the information, such as jitter and accuracy of coreclock, is not available for some reason.

    Please go ahead and close the ticket.

    Just as a side note, Timing Analyzer does in fact report coreclockout as a separate clock to the incoming PCIe_ref clock pin (as opposed to one generated by it).