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corestar's avatar
corestar
Icon for Contributor rankContributor
2 years ago

How is PCIe coreclkout_hip generated?

I'm using a Cyclone V GT PCIe Avalon ST core. It might be helpful to use coreclkout_hip to run our application layer, but it is not clear how that clock is generated and how much jitter it has. I ha...
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate and get back to you soon. Thanks for your patience.

Best regards,

Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,

    Yes you are correct, the coreclkout_hip source is from PCIe HIP.
    if you are referring to PCIe Protocal Jitter specification, total Jitter for

    1. Pcie cable - 100 ps
    2. PCie gen1 - 100 ps
    3. Pcie gen2 - 50 ps

    Detail information about the jitter spec, you may get from Cyclone V Characterization Report.
    But I don't think you can obtain the report from public release platform.
    IF you have access to Intel Premium Support (IPS) you may file an ticket to get it as well or You may contact your Intel Distributor as alternative.

    Regards,

    Wincent_Intel

    • corestar's avatar
      corestar
      Icon for Contributor rankContributor
      2 years ago

      Hello,

      Yes you are correct, the coreclkout_hip source is from PCIe HIP.

      Are you saying the PCIe HIP has a clock generator independent of incoming PCIe refclk?

      Are there any specs on it's jitter and accuracy? I'm thinking of using it instead of an external clock.

      I'm familiar with the PCIe jitter specs, but if the coreclockout_hip is generated from refclk, I was wondering about the situation where PCIe Spread Spectrum is enabled (the norm on many systems) as described here:

      PCIe Spread Spectrum Clocking

      In this case, refclk is modulated with a 35 KHz triangle wave and the incoming PCIe refclk itself has very high jitter. Apparently has high as 4ns. This is on purpose to reduce EMI.

      The PCIe IP itself is designed to handle it, but other parts of a system are not and depend on low jitter.

      Thanks

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        2 years ago

        Hi,

        Based on my understand via PCIe Specification, please correct me if you feel I am wrong

        1. Refclk (Reference Clock): This is typically provided externally to the FPGA and is used by the PHY to synchronize the transmission and reception of data. In spread spectrum mode, as you mentioned, the frequency of this clock is modulated slightly to reduce electromagnetic interference (EMI). The amount of jitter on this clock can indeed be significant, especially in spread spectrum mode.

        2. Coreclkout (Core Clock Output): This clock is generated by the FPGA's hard IP, usually from a stable internal reference clock source. It's typically used to clock the internal logic of the FPGA design, including any user logic interfacing with the PCIe core.

        Not sure this able to help you or not, let me know if you have any other question.

        Regards,
        Wincent_Intel