How do I access the Intel® 'Cyclone V GX' DDR3 hard memory controller 'Configuration and Status Interface'?

Hi VBotn,

I can see your confusion from EMIF handbook statement "This interface is clocked by csr_clk, which is the same as afi_clk, and is always synchronous relative to the main data slave interface.".

What this statement meant is simply both clock are sync to EMIF IP data interface and not saying both clock are operating with same frequency. I am sorry as the statement is misleading.

Yes, csr_clk is input clock source for EMIF IP config and status register interface. It's meant to be low speed control interface clock coming from FPGA core clock network. We don't really specific min/max clock spec for it but I would advise 100MHz clock as general guideline.

Thanks.

Regards,

dlim