The device must capture the destination address from the first config transaction it receives and store it for use in outgoing transactions. Since PCIe is actually point-to-point, not a bus, a device only receives config transactions that are intended for it.
Means when RP send the configuration first read or write transaction to endpoint, the endpoint save the bdf set in config read/write transaction and use it later.
jeff_zhu
New Contributor
New ContributorHow can the user logic obtain the bus number and device number from the Agilex R-tile AVST PCIe IP?
The user logic needs to obtain the bus number and device number to generate TLPs for mem-read request, but there isn't TL interface as in P-tile IP to get the enumerated bus number and device number. I can't find them in configuration space either
Hi Jeff,
In P-tile, the bdf is available in tlp config, but not in R-tile.
the RTL is encrypted, Hence not much information I can obtain from that.
What I get from the official release document for R-tile AVST will be.
https://www.intel.com/content/www/us/en/docs/programmable/683501/22-3-7-0-0/about-the-r-tile-streaming-fpga-ip-for.htmlbus#, device# are discovered by RP during enumeration process, only the RP host side can read the bus#, device#
Detail, you may refer to B. Root Port Enumeration
Hope this answer your question.
Regards,
Wincent_Intel
