The device must capture the destination address from the first config transaction it receives and store it for use in outgoing transactions. Since PCIe is actually point-to-point, not a bus, a device only receives config transactions that are intended for it.
Means when RP send the configuration first read or write transaction to endpoint, the endpoint save the bdf set in config read/write transaction and use it later.
Forum Discussion
jeff_zhu
New Contributor
New ContributorHow can the user logic obtain the bus number and device number from the Agilex R-tile AVST PCIe IP?
The user logic needs to obtain the bus number and device number to generate TLPs for mem-read request, but there isn't TL interface as in P-tile IP to get the enumerated bus number and device number. I can't find them in configuration space either
Hi Jeff,
In P-tile, the bdf is available in tlp config, but not in R-tile.
the RTL is encrypted, Hence not much information I can obtain from that.
What I get from the official release document for R-tile AVST will be.
https://www.intel.com/content/www/us/en/docs/programmable/683501/22-3-7-0-0/about-the-r-tile-streaming-fpga-ip-for.htmlbus#, device# are discovered by RP during enumeration process, only the RP host side can read the bus#, device#
Detail, you may refer to B. Root Port Enumeration
Hope this answer your question.
Regards,
Wincent_Intel
7 Replies
Wincent_AlteraRegular Contributor
Hi,
Thank you for reaching out.
Just to let you know that Intel has received your support request and I am assigned to work on it.
Allow me some time to look into your issue. I shall come back to you with findings.
Thank you for your patience.
Best regards,
Wincent_intel
- Wincent_Altera
Hi,
Can you clarify more about what you trying to look at?
If you need to obtain the bus and device number you can try the command $ lspci -vt
For the R-tile configuration space register you may refer link below
Hope this answers your question
Regards,
Wincent_Intel
- Wincent_Altera
Hi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
jeff_zhuHi, Wincent,
What I want to know is how to get the bus and device number is the FPGA user logic, from the IP interfaces of AVST for R-tile PCIe. In PCIe TLP, these numbers are needed. I'm not asking how to get them with linux command.
- Wincent_Altera
Hi Jeff,
The device must capture the destination address from the first config transaction it receives and store it for use in outgoing transactions. Since PCIe is actually point-to-point, not a bus, a device only receives config transactions that are intended for it.
Means when RP send the configuration first read or write transaction to endpoint, the endpoint save the bdf set in config read/write transaction and use it later.
In P-tile, the bdf is available in tlp config, but not in R-tile.
the RTL is encrypted, Hence not much information I can obtain from that.
What I get from the official release document for R-tile AVST will be.
https://www.intel.com/content/www/us/en/docs/programmable/683501/22-3-7-0-0/about-the-r-tile-streaming-fpga-ip-for.htmlbus#, device# are discovered by RP during enumeration process, only the RP host side can read the bus#, device#
Detail, you may refer to B. Root Port Enumeration
Hope this answer your question.
Regards,
Wincent_Intel
- Wincent_Altera
Hi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
