Forum Discussion
Hi @AhmedH_Intel ,
Thanks for the response.
Here is the system level information.
architecture (system) path :
Host driver will write configuration & data from PCIe (Bar4) which is connected to QSPI IP ( avl_csr & avl_mem ) ports.
Sequence i followed is provided from intel quad spi document (page num 26) : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf
proc page_program { } {
global mp operating_protocols_setting control_register write_instr
master_write_32 $mp $operating_protocols_setting 0x00000222 //qspi configuration register (avl_csr port) to select 4 byte enable
master_write_32 $mp $control_register 0x00000101 //qspi configuration register (avl_csr port) to enable output
master_write_32 $mp $write_instr 0x00007034 //qspi configuration register (avl_csr port) for write instruction command on flash memory
master_write_32 $mp 0x00001000 0x1234abcd //qspi memory access port (avl_mem port) writing single DWORD into FLASH MEMORY
}
Problem statement : I am able to get the address (0x00001000) and data (0x1234abcd). But unable to get the command. Command is required to come first before address & data.
Not able to get the proper sequence from intel. Can you help me out for it?
Thanks in advance