How can I troubleshoot two Triple Speed Ethernet IP's on an Altera MAX10 FPGA?

Hi Mansur, You may want to try with lower level debug on TSE MAC first. Example like performing loopback testing to see where is the failure point. 1) Loopback within TSE IP 2) Loopback on External PHY chip 3) Then only finally loopback on external host second FPGA side. If loopback is working then most likely is your higher level software application layer issue. Sim working is a good sign. That tell you most likely the setting is correct. Then you can compare what's difference on sim vs actual hardware like how do you sim external PHY and second FPGA ? Could the problem resides there ? Thanks. Regards, dlim