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3 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor

    Hi Kokodo,


    Every time the reset is triggered, the EMIF IP will perform the calibration process.

    After the calibration process has finished, the user can access the controller.


    So far the user can only interact with DDR by performing write and read transaction through EMIF IP.

    I don't think we can initialize the data through EMIF IP. It's need to write through Avalon Memory Mapped Interface.


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor

    As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.