How can I connect PCI Express MegaCore to FIFO!

Transfer of data can happen in either direction for either a Master (PCIe spec actually uses the term Initiator) or a Slave (PCIe spec actually uses the term Completer).

If the FPGA with the PCIe port was a completer only (slave only) the PC could transfer data to the FPGA by using Write operations and the PC could transfer data from the FPGA by using Read operations. Now if the FPGA also has initiator (master) capabilities, then it could transfer data to the PC memory by using writes it initiated. It could transfer data from the PC memory by using reads it initiated.

The example design and testbench created by PCI Express Compiler demonstrates both of these modes of operation.

Unfortunately I don't have any PC software application source code to provide as an example. I think the Altera Stratix II GX PCIe Develoment Kit does have a software application that demostrates this, but source code is not available.