How can I connect PCI Express MegaCore to FIFO!

On the PCI Express link you are still going to need an address, any PCI Express Switches in the system need to know how to route requests to your device as opposed to other devices in the system. So you will still need a BAR, you can set it to be the smallest size possible. Your BIOS or OS will assign an address to this BAR and that is the address you will use in your software application to access the FIFO.

Now if your endpoint only has the FIFO in it, you can ignore the addresses in your logic design. Any Read and Write requests received from the PCIe link can be used to access the FIFO. If you design it that way then from the software application any address that matches the BAR can be used to access the FIFO.