Hi, I'm trying to make a delay instruction in verilog, I have an output (PWM) and I want to generate another output (PWM1) from PWM but with a delay: i tried this : assign #50 pwm1 = pwm; but it's not working best regards,

Do get a 100ns delay it depends on your clock period. If it is 20ns (50MHz) then a 5 stage D FF shift register will delay a signal by 100ns (5 clock periods).

You can easily code this in verilog or Altera even has an IP block you can use (ALTSHIFT_TAPS, but it is really overkill for what you need to do).