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Altera_Forum
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18 years ago

Help! Implenting a Cmex S-functions into your FPGA

Hello all I was wondering if any one has managed to get Signal compiler in simulink to actually compile and convert your S-function to VHDl. I have completely hit a dead end and cant find ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

This is a DSP Builder 7.0 design. I would strongly recommend you upgrade to DSP Builder 7.2. DSP Builder was completely rewritten in 7.1 and 7.2 and its service packs have further improvements. My previous comments in this thread assumed you had 7.1 or 7.2 so it's not surprising they weren't so useful.

As to your compile error it's because this line appears in the generated source:

assert (1<0) report altversion severity Note;

Since 1 is rarely less than 0, this file will not compile. I don't have DSP Builder 7.0 so I can't tell you why this happens.