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Altera_Forum
Honored Contributor
Honored ContributorHelp! Implenting a Cmex S-functions into your FPGA
Hello all I was wondering if any one has managed to get Signal compiler in simulink to actually compile and convert your S-function to VHDl. I have completely hit a dead end and cant find ...
Altera_ForumHonored Contributor
Honored ContributorThe best I can do is to point you to the user guide:
http://www.altera.com/literature/ug/ug_dsp_builder.pdf Look for chapter 9 and explicit black box interfaces. Other than that I would suggesting posting your design - it's hard to say what's wrong without a simulink model.
