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JJame30's avatar
JJame30
Icon for New Contributor rankNew Contributor
6 years ago

Hello, "# Fatal error in Process MEMORY at C:/altera/12.1/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 39940". how to proceed? can you suggest a proper way to simulate my top level vhdl code?

I am working on interfacing Stratix 4 GX FPGA with DDR2. I used uniphy ip core in Megawizardpulgin tool. I got full files and i simulated example design with provided testbench (in modelsim). its wo...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

Thanks for your interest in using FPGA products but I also would like to share with you Stratix IV FPGA is a legacy product while Quartus v14.0 is too old, obsolete version.

My advice to you as below

  • Sorry but I foresee it's unlikely to get any hands on training for legacy FPGA product. I propose to migrate to newer generation of FPGA product if possible like the 10th series FPGA family - Cyclone 10 GX for instance to get better technical support
  • Yet, if you still prefer Stratix IV FPGA then feel free to checkout below online training course (some are free, some are paid service)
  • https://www.intel.com/content/www/us/en/programmable/support/training/legacy.html
  • Or you can also google for the IP user guide doc as well
  • Another thing to take note is to upgrade to latest Quartus version if possible (v19.1 standard edition) as v14.0 is already obsolete.

Thanks.

Regards,

dlim