Forum Discussion

JJame30's avatar
JJame30
Icon for New Contributor rankNew Contributor
6 years ago

Hello, "# Fatal error in Process MEMORY at C:/altera/12.1/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 39940". how to proceed? can you suggest a proper way to simulate my top level vhdl code?

I am working on interfacing Stratix 4 GX FPGA with DDR2. I used uniphy ip core in Megawizardpulgin tool. I got full files and i simulated example design with provided testbench (in modelsim). its wo...
JJame30's avatar
JJame30
Icon for New Contributor rankNew Contributor
6 years ago

Hello,

Currently we are doing a project which focus on SFPDP, DDR2, SATA

Tool: Quartus II(14.0), Modelsim (vhdl)

FPGA: Stratix 4 GX

We are planning to use ALTGX, ALTGX_RECONFIG, UNIPHY etc. mega functions for the development of the system. We would like to have proper guidance for doing this.

Can you provide 1-2 weeks hands on training on above mentioned IP cores? or the procedure for doing so.