HDMI Output Settings

HI Johnson,

All the clocking conversion for different HDMI resolution is typically handled by the reconfig controller design algorithm of the HDMI example design.

Cyclone 10 GX only support 2 symbol for clock mode

There are 3 main clocks used by HDMI Ip example design.

1. pixel clk = Total_Horizontal_Pixels * Total_Vertical_Pixels * Refresh_Rate
2. vid_clk used by FPGA core VIP design = the clocking setting vary depend on symbol per clock and pixel clock
3. ls_clk used by HDMI IP = the clocking setting vary depend on vid_clk and bit per colour (bpc)

Note : refer to below HDMI user guide doc page 76 (table 36 - HDMI source interface) for the detail explanation.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_hdmi.pdf

Another quick guideline with summary table can be found in same user guide doc, page 37 (table 15 : HDMI PLL Desired Output Frequencies for 8-bpc Video)

• You can just refer to the 2 symbol per clock section for Cyclone 10 GX device
• TMDS bit rate or transceiver data rate per channel can be derived from HDMI per channel bandwidth calculation
  • BW = pixel clock * (bit per colour + 2)

Thanks.

Regards,

dlim

Hi Johnson,

I have shared with you the PLL output ls_clk and vid_clk formula in previous update.

the detail explanation is captured in HDMI user guide doc page 76 (table 36 - HDMI source interface)

Thanks.

Regards,

dlim