HDMI IP core timing problems

Hi jdeffenb,

We are having somehow similar issues. Have you managed to resolved yours? In particular, have you had to add new timing constraints to the design?

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Hello,

I am trying to incorporate the HDMI 2.0 core onto an Arria 10 device (Quartus 17.0) and am having trouble with what I believe to be timing problems. The core worked great for TX, and was a little picky with RX on my original build. After incorporating the rest of the project which includes 8x GEN3 PCIe and a 10Gbps SFP+ transceiver, I am getting erratic behavior between builds. Sometimes no HDMI output, sometimes lower resolutions like 1080p will work but not 4k@30 and sometimes visa versa. When I say no output, I mean the monitor cannot detect a signal, I do see data going by with the scope. HDMI RX is also not working right, in that the core will not show vid locked. The only constraints I have in place for the HDMI portion are the ones automatically generated and the input clock of course. In addition to erratic behavior on the HDMI output, I also have trouble with my pixel clock randomly between builds. Pixel clock is generated from IO PLL and it sometimes outputs the wrong frequency (divide by 4 instead of 2 for example), and it will not recover between power cycles or recal. I am also experiencing long compile times ~50min not sure if that is normal or not for a project this size, or if that is evident of constraint problems?

Any advice as to where I should be looking for problems?

Thanks

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