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M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro

Hi support, When creating a design with "HDMI Intel FPGA IP" having significant values as: - Direction: Receiver - Enable Active Video Protocol: AXIS-VVP Full - Support FRL: Untick (disabled) Th...
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  • Wincent_Altera's avatar
    Wincent_Altera
    1 year ago

    Hi @M_DK_FPGA ,

    I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
    However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
    Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.

    Currently AXI Bridge is setting to 16BPS (16x3 48bits).
    If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
    Detail about the implementation you may refer to
    Hope that able to help you to move a step forward, let me know if further clarification is needed.

    Regards,
    Wincent_Altera
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi @M_DK_FPGA ,

I was able to replicate your issue as mentioned in 2 March 2025 reply.

try to disable AUX and deep color the AXIS-VVP full by default disable again in new generated HDL.
When remove the deep color at the IP core in Arria 10 in example design generation , we seeing the same error as yours.



I understand your frustration, Please do believe that I am trying my best to ensure your success.
Also, i do understand your concern, I am working with our design team to fix this issue. But the investigation may take longer time.

You can ignore the request to having IPS on this.
I will raise the support level in to higher level, hope we can get some investigation result back soon.
Please accept my apology if for the inconvenience cause to you.

Regards,
Wincent_Altera

M_DK_FPGA's avatar
M_DK_FPGA
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Wincent_Altera,

Thanks for getting back to this so quickly, and it is reassuring that you see the same tool behaviour.

It sounds good you will elevate the support case, if you concurs that there may be a problem in the HDMI core IP.

I am looking forward to any further updates.

Regards
M_DK_FPGA

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi @M_DK_FPGA ,

    I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
    However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
    Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.

    Currently AXI Bridge is setting to 16BPS (16x3 48bits).
    If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
    Detail about the implementation you may refer to
    Hope that able to help you to move a step forward, let me know if further clarification is needed.

    Regards,
    Wincent_Altera
  • M_DK_FPGA's avatar
    M_DK_FPGA
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi Wincent_Altera,

    OK, thanks for the suggested workaround, and I see the point that the AUX and Deep Color features can be disabled by just tying the interface to constants, whereby synthesis will remove the idle design part.

    However, I still assume that disabling the features in the interface should not break synthesis, nor make output in-stable (blank most of the time), which may be relevant only to other users of the core, now that you have pointed out a possible workaround.

    Please feel free to close the case if you think it is covered.

    Regards
    M_DK_FPGA

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi @M_DK_FPGA ,


    First and foremost, I would sincerely apologies that the workaround take unexpected delivery time.
    Please believe that, I am trying my best to ensure you and all of my client success.


    Feel free to try out those workaround, if you facing any issue or anything need to be further clarified, please post a new forum.
    If you need specific my support, you may point out my name "Wincent" in the description, It will be pleasure there to support you again. Hope this help to accelerate your current project progress.

    Regards,
    Wincent_Altera

  • M_DK_FPGA's avatar
    M_DK_FPGA
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi Wincent_Altera,

    Thank you for your thoughtful response and your generous offer of future support—it is truly appreciated.

    I will accept the suggested workaround as the solution and will post a new question in this forum if any further issues arise.

    Best regards,
    M_DK_FPGA