Nagaraju
New Contributor
2 years agoHDCP in "HDMI Intel FPGA user guide"
I haven't found any details in document "HDMI Intel FPGA user guide" about how HDCP encrypts and decrypts the video . I do have few questions below which needs to be addressed.
Question: As hdcp cipher(see hdcp v2.3 spec(HDMI)) encrypts/decrypts five pixel at a time, there could be a problem when partial pixels(less than 5 pixels, for example 3 pixels) left and when vsync asserts after few clock cycles. This can pause feeding the available 3 pixels to hdcp cipher till vsync asserts. How this situation is handled?