Forum Discussion
Occasional ContributorHBM2 interfacing with the PCI express hard IP STRATIX 10 MX
Hi, Sorry for the mistake.
I tried the same and I only can see the 16bits on the address. These address bits are affected by the setting of "Address width of bursting master" of the PCIe IP. I believe the developer hack the IP and change the address width to 30 instead.
If you need, you can change this by modifying the g3x16_hbm2_avmm_bridge_512_0.ip file.
Search for Address width of Bursting Master and you can change the value to 30.
Occasional ContributorHi @BoonT_Intel ,
Thanks for the reference design. I changed the device to 1sm21chu2f53e2vg which is the device I have along with the HDL changes required and PIN assignments. I have not changed anything else. But I am getting this warning now.
Warning(332049): Ignored create_clock at pcie_to_hbm2_ddr4_top.sdc(2): Incorrect assignment for clock. Source node: REFCLK_GXBL1C_CHTP already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated.
Info(332050): create_clock -name {REFCLK_GXBL1C_CHTP} -period "100Mhz" [get_ports {REFCLK_GXBL1C_CHTP}]
REFCLK_GXBL1C_CHTP is the iopll reference clock for HBMC. Can you tell me what can be the reason for this as according to me it is just defined in the project sdc file once.
Occasional ContributorHi @BoonT_Intel, please I have been working on the reference design that you provided. There are a few bugs that I found in one of the files but the design is still not working. I am attaching the updated file here. I suspect there are other problems with it too.
Can you please tell me when will the final design be posted after validation? Hoping that all the bugs will be removed by then.
Also, can I do something to accelerate this process?
Thanks.
BoonT_IntelFrequent Contributor
Hi Sir,
Due to the pandemic, we having the challenge to access the hardware to test the design.
I will get back to you once it tested.
By the way, are you also seeing the problem if you just compile the design without making any changes?
- rsing108
Hi @BoonT_Intel ,
Yes, I am seeing the problem when I compile without making any changes. I also ran simulations where one can see that many important/necessary axi4 signals to the HBM2, as I mentioned in my previous comment are not even being driven because of the problems with the source code.
- BoonT_Intel
ok in this case we should able to spot the problem when we validate the design.
jg_UFNew Contributor
Hi @BoonT_Intel ,
I am a student from the same lab as @rsing108 , picking up this project where he left off. Has there been any update with this design validation?
We are specifically interested in the axi_bridge_to_hbmc_if.v design file, as we are still encountering issues in our own derived design that we think may be due to undiscovered bugs in this file.
Thanks!
