rsing108
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Re: HBM2 interfacing with the PCI express hard IP STRATIX 10 MX
Hi @BoonT_Intel , Yes, I am seeing the problem when I compile without making any changes. I also ran simulations where one can see that many important/necessary axi4 signals to the HBM2, as I mentioned in my previous comment are not even being driven because of the problems with the source code.4.6KViews0likes1CommentRe: HBM2 interfacing with the PCI express hard IP STRATIX 10 MX
Hi @BoonT_Intel, please I have been working on the reference design that you provided. There are a few bugs that I found in one of the files but the design is still not working. I am attaching the updated file here. I suspect there are other problems with it too. Can you please tell me when will the final design be posted after validation? Hoping that all the bugs will be removed by then. Also, can I do something to accelerate this process? Thanks.4.7KViews0likes4CommentsRe: HBM2 interfacing with the PCI express hard IP STRATIX 10 MX
Hi @BoonT_Intel , Thanks for the reference design. I changed the device to 1sm21chu2f53e2vg which is the device I have along with the HDL changes required and PIN assignments. I have not changed anything else. But I am getting this warning now. Warning(332049): Ignored create_clock at pcie_to_hbm2_ddr4_top.sdc(2): Incorrect assignment for clock. Source node: REFCLK_GXBL1C_CHTP already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated. Info(332050): create_clock -name {REFCLK_GXBL1C_CHTP} -period "100Mhz" [get_ports {REFCLK_GXBL1C_CHTP}] REFCLK_GXBL1C_CHTP is the iopll reference clock for HBMC. Can you tell me what can be the reason for this as according to me it is just defined in the project sdc file once.4.7KViews0likes5CommentsRe: HBM2 interfacing with the PCI express hard IP STRATIX 10 MX
Hi @BoonT_Intel , I am currently stuck. It would be great if you could get me the design. Also, if possible can you get this design for 1sm21chu rather than 1sm21bhu? if not then 1sm21bhu is also fine. Thanks for your help.4.8KViews0likes0CommentsRe: HBM2 interfacing with the PCI express hard IP STRATIX 10 MX
Thanks @BoonT_Intel , it indeed appears that this a some kind of a hack by the developer. Thanks! One a side note, can you refer me to maybe an example design/reference design where I can understand the working/usage of multiple BARS?4.9KViews0likes0CommentsRe: HBM2 interfacing with the PCI express hard IP STRATIX 10 MX
Thanks @BoonT_Intel for the reply. The difference in size is for the BAM_master address of PCIE IP and not the HBM ip. Also the CHU one has 30 bit address in the reference design and chu has 16 bit address for the same PCIE hard ip+ configuration.4.9KViews0likes1Comment