Forum Discussion
Occasional ContributorHBM2 interfacing with the PCI express hard IP STRATIX 10 MX
Hi, Sorry for the mistake.
I tried the same and I only can see the 16bits on the address. These address bits are affected by the setting of "Address width of bursting master" of the PCIe IP. I believe the developer hack the IP and change the address width to 30 instead.
If you need, you can change this by modifying the g3x16_hbm2_avmm_bridge_512_0.ip file.
Search for Address width of Bursting Master and you can change the value to 30.
Frequent ContributorHi Sir,
Due to the pandemic, we having the challenge to access the hardware to test the design.
I will get back to you once it tested.
By the way, are you also seeing the problem if you just compile the design without making any changes?
Occasional ContributorHi @BoonT_Intel ,
Yes, I am seeing the problem when I compile without making any changes. I also ran simulations where one can see that many important/necessary axi4 signals to the HBM2, as I mentioned in my previous comment are not even being driven because of the problems with the source code.
- BoonT_Intel
ok in this case we should able to spot the problem when we validate the design.
