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Knug's avatar
Knug
Icon for Contributor rankContributor
4 years ago

Has anyone else used 1 PFL for "programming flash + FPGA configuration", FFPx16 & got it to work ?

Having issues getting 1 PFL solution for programming flash + FPGA configuration using FFPx16 PLF within CPLD MAXV. PFL connected to CFI Flash device FPGA to configure: Cyclone V --- We have a...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Kevin,


Is it possible for you to send us the design for further debug? You can reply to the email sent to you from supportreplies@intel.com dated 12th April.


Meanwhile can you please confirm that the flash_access_granted pin of the PFL IP is driven to '1' when flash_access_request is asserted.


Regards.


  • Knug's avatar
    Knug
    Icon for Contributor rankContributor
    4 years ago

    I have rectified my issue by myself. pfl_nreset had to be delayed from 0 -> 1 using a counter within my wrapper to get the FPGA to configure successfully right after flash programming.

    flash_access_granted pin of the PFL IP is driven to '1' when flash_access_request is asserted because I had flash_access_request (out) connected to flash_access_granted (in) internally within the wrapper.