GTS SDI II IP Core...what is the tx_vid_clkout frequency

Hi aucamera1​ 

Thank you very much for your very quick answer.

I checked in the new version of Quartus 26.1 and there's no change.

Maybe my problem is not exactly the same as you at the end. I have my own electronic board with two VCXO to provide a 100 MHz input clock (for GTS System PLL) and a 148.5 MHz input clock (for TX PHY PLL). For now I faced two scenarios :

1. When I use pins REFCLK_GTS_CH1P/N pins for 148.5MHz reference clock and pins REF_GTS_RX_P/N pins for 100 MHz reference clock, my system behaves as you described in your ticket : the PHY TX PLL locks but the frequency is not correct.
2. When I use pins  REFCLK_GTS_CH1P/N pins for 100 MHz reference clock and pins REF_GTS_RX_P/N pins for 148.5 MHz reference clock (swapping pin locations in QSF file and swapping my VCXO configurations), the PHY TX PLL sometimes locks (and TX CLOCK OUT is 74.25 MHz as excepted) but most of time it does not lock.

Unfortunately I cannot provide a 297 MHz clock because my VCXO are limited to 250 MHz.

I did create my SDI sub-system based on exemple design generated by Altera (in mode "Both Base and PHY") and the example design (signal names and clock constraints in SDC file) seems to expect a 148.5 MHz reference clock for TX PHY. But it does not mean it will work with this frequency, I cannot easily test this example design on my electronic board.

I am going to continue my investigation keeping in mind all your remarks. I will try to use option "Base only" option with an external GTS PMA/FEC Direct PHY IP. When I generate an example design in this mode, indeed, I can configure the reference clock frequency for TX PHY PLL (which is configured to 148.5 Mhz by default, both for 25.3.1 and 26.1 versions of Quartus).

Thanks again for you very fast reply.

Regards

Xavier