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aucamera1's avatar
aucamera1
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5 months ago

GTS SDI II IP Core...what is the tx_vid_clkout frequency

I'm using an Agelix 5 (the Altera development board) with Quartus Pro 25.3.1 w/patch 1.02. i'm trying to set-up the GTS SDI II IP Core (version 2.3.0) on the Main screen, the only configurable valu...
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xcrouzy's avatar
xcrouzy
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13 days ago

Hi aucamera1​ ,

I found your topic about TX PLL lock issue with GTS SDI II IP.

I'm writing to ask if you've solved your problem, as I'm currently experiencing the exact same issue (same version of Quartus, same version of IP) : the lock signal is asserted, the tx_ready signal is asserted but the TX clock out frequency is not 74.25 MHz as expected.

Thanks in advance for your answer.

Best Regards

Xavier

aucamera1's avatar
aucamera1
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13 days ago

Hi Xavier,

the answer is buried in the chain above, but its a bit confusing to follow (i'll go back and mark the solution post to see if that helps).

basically, the GTS SDI II IP, when "Wrapper Options >> SDI_II wrapper" is set to "both Base and PHY", then the txpll_refclk input clock must be 297MHz.  If you set the wrapper to Base only, then you can configure that clock but you have to use the GTS PMA/FEC Direct PHY IP as well.

I can't remember exactly at the moment, but there were issues with me getting that 297MHz clock to the pin when using the "both".

IMHO.....I think they set that "both" wrapper up using an eval board that had a 297MHz on a daughter card and left it in there.  It doesn't make sense to require that high of a frequency clock to be produced simply because of a setting variable gets hardcoded when they combine the two IPs.  Hopefully they fix this in a future revision