kharitonow
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New ContributorGTS DirectPHY simple simulation VHDL
Hello everyone, I'm trying to do a simple GTS Direct PHY simulation in VHDL. I've created a simple design in platform designer to try out the GTS transceivers in a serial loopback mode: As one...
Hi,
Few things to checkout first.
1) Are the Tx and Rx serial lines connected at the testbench? Rx lines must have data incoming on it at the configured data rate for it to lock to data and to assert rx_ready signal.
2) Check the reference clock frequency to the system pll.
3) If all the connections are correct and the input clock frequencies are also as configured in the IP, then try running it for some more time. Run upto 1ms and see.
Regards
