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pnp
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4 years ago
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GPIO DDRIO IP output swapped: datainhi/datainlo inverts forwarded clock

I have a source-synchronous interface for which I am forwarding a clock with a DDRIO register as recommended in AN433 pp6-7 to minimize skew between the clock and data waveform: I created a ...
pnp's avatar
pnp
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4 years ago

Looking at the very bottom of ug_altera_gpio.pdf there is this note:

I feel like this is a clue, though this paragraph is as clear as mud to me. In my case I did not migrate the IP, I am not using the legacy top-level port names, and the port meaning in that bullet list is what I expect the IP to do.