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pnp
New Contributor
New ContributorGPIO DDRIO IP output swapped: datainhi/datainlo inverts forwarded clock
I have a source-synchronous interface for which I am forwarding a clock with a DDRIO register as recommended in AN433 pp6-7 to minimize skew between the clock and data waveform:
I created a ...
Hello Paul,
We have checked the design. We think it may be because of your coding design. We switched your 10 to 01 and got this result. Is this what you are expecting?
Image 1: Waveform
Image 2: Design
Image 3: Reference from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf
Thank you.
pnpNew Contributor
New ContributorLooking at the very bottom of ug_altera_gpio.pdf there is this note:
I feel like this is a clue, though this paragraph is as clear as mud to me. In my case I did not migrate the IP, I am not using the legacy top-level port names, and the port meaning in that bullet list is what I expect the IP to do.
