Forum Discussion
HI,
I am not sure which FPGA and which board that you are trying to run your test here but you can always start with reference design.
Just search for "simple socket server" from below Intel FPGA design store for some reference design as guidance.
If reference design also failed then you can proceed to debug if something is wrong with TSE IP design using loopback check
- You can start with external loopback on the on board PHY chip if possible
- After that you can test the loopback in TSE IP to slowly isolate where is the problem
Thanks.
Regards,
dlim
- sRama286 years ago
New Contributor
Thanks Dlim
i am using MAX 10 plus board .i got sample code from terasic it is working properly which is configured as RGMII mode.but i want to change to MII (10/100 MBPS).
Q1. what are the changes i should do for that.please clarify........................
i have changed tse_my_system.c file
terasic file for RGMII:
alt_tse_system_info tse_mac_device[MAXNETS] = {
TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(TSE_MAC, 0, SGDMA_TX, SGDMA_RX, TSE_PHY_AUTO_ADDRESS, &marvell_cfg_rgmii, DESCRIPTOR_MEMORY)
replaced marvell_cfg_rgmii to 0 like below
alt_tse_system_info tse_mac_device[MAXNETS] = {
TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(TSE_MAC, 0, SGDMA_TX, SGDMA_RX, TSE_PHY_AUTO_ADDRESS, 0, DESCRIPTOR_MEMORY)
but PC is not connected to board via telnet .
Q2. i want change any setting in eclipse?
please help me.......