Fundamental question about Jesd204B, Lanes VS ADCs

Dear Intel Support/Expert

I have a fundamental question while I am working on Jesd204B IP.

I need to use Arria 10 GX develop board, to implement a 64 channels ultrasound system.

the basic idea is. use 4 TI AFE58JD48, each one is configured to 4 lanes, 16 ADC, 16 bits resolution, so LMF = 4X16X8. assume use 6144M lane speed. and 76.8M pll/CDR reference clock frequency.

per my understanding, for 4 lanes support 16 ADC X 16 Bits = 256 bits, each lane(frame) corresponds to 64 bits. TI AFE58JD48 has an 80X mode. which means sample clock = lane rate / 80, in this case, 76.8M sample clock.

but in Intel Jesd204B IP, each lane fixed to 32bits(frame). which means it only support 40X mode. which means sample clock = lane rete / 32(if ignore the 8b/10b).

I assume that if I set the TI AFE58JD48 to 80X mode( LMF = 4X16X8, each frame has 8 octets). set Intel IP core to X40 mode( LMF = 4X16X4, each frame has 4 octets).

Is it possible that Intel Jesd204B receiver uses two clocks to extract 8 octets frame to 2 4-octets frames.

if not, what is the best option to transfer 16 ADCs( 16 bits resolution each ADC) through 4 Jesd204B lanes?

Appreciate your help,

Sincerely,

David