Fundamental question about Jesd204B, Lanes VS ADCs

Hi David

I assume that if I set the TI AFE58JD48 to 80X mode( LMF = 4X16X8, each frame has 8 octets). set Intel IP core to X40 mode( LMF = 4X16X4, each frame has 4 octets).

>> Is possible. The two reference designs below looks similar.

In the Stratix 10 example design, the TI wideband ADC12DJ3200 device is the 12-bit converter which is capable of operating

at up to 3.2 giga samples per second (Gsps) in dual channel mode or 6.4 Gsps in an interleaved single channel mode. This design is programmed to run at the fastest sample rate of 6.4 Gsps in single channel mode, where this mode effectively interleaves the two analog-to-digital converter (ADC) channels together to form a single channel ADC at twice the sampling rate.

1) AN803: Implementing Synchronized ADC Multi-Link Design with JESD204B RX IP Core

https://www.intel.com/content/www/us/en/design-example/714466/arria-10-an803-implementing-synchronized-adc-multi-link-design-with-jesd204b-rx-ip-core.html

2) AN833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

https://www.intel.com/content/www/us/en/docs/programmable/683049/current/gx-16-lane-rx-jesd204b-adc12dj3200-interoperability.html