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ADmcj
New Contributor
New ContributorFunctional test of the FFT IP
Hi all, I would like to test the FFT IP. As such I tried to use the example that is generated with the IP parameter editor (quartus 17.1), but it generates only stuff in verilog while I need vhdl. ...
vj123New Contributor
New ContributorHi,
- While Configuring parameters of FFT IP use "Generate HDL.." tab & choose VHDL under Synthesis & Simulation.
- Check output Directory path.
- Then click on "Generate"
- Use that generated .vhd file under Synthesis Directory as a design under test(DUT) in ModelSim & write a test bench for simulation if you don`t want to simulate it using TCL script.
5. If you want use Automated test bench then use NativeLink.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards
Vikas Jathar
