FPGA freeze while using remote update IP - Cyclone V

Update -

I did some digging, and finally got the block to work.

I've prepared a checklist to debug the core:

1. Make sure the design which has the factory configuration is in remote mode. Choose the correct configuration method (ASX1, ASX2).

2. Check configuration pins on the board -- nSTATUS, nCONFIG, config_done - See that the pins are pulled high/low. Check for voltage and resistor values on the device handbook.

3. Check MSEL pins on the board - Depending on the configuration scheme you use, pull it high/low with appropriate resistor values - check the device handbook for more details.

If either of these are not set correctly, the remote update block WON'T work.

This would be a nice debug strategy to follow, if the IP fails in spite of all the above mentioned things are OK.

1. Most of the reference designs don't have POF checking ON. Use POF checking and mux the pins with the ASMI address, dataout and data valid signals.

Debug: Use signal tap or any other method to probe POF error signal. If the signal is high, the application configuration is not written to the flash at the desired address.

2. If watchdog is enabled, you will have to PERIODICALLY reset it in the application image.

Debug: Disable the watchdog and see if the application image is up. If yes, enable the watchdog in the factory image. In the application image, you will have to reset the timer periodically.

The frequency at which the timer is reset must be greater than the frequency at which the watchdog times out. This should get the IP working.

Hope this helps.

Kamath