For the life of me, I cannot find the document that describes byte-write limitations in Arria 10 DDR3 hard ip emif. I'm looking for the table that describes how the DM lines can and cannot be grouped in a x64 interface. Thank you.

My mistake... the question I had is Avalon related, not hard memory controller. I was looking for the following:

-begin

When more than one bit of the byteenable

signal is asserted, all asserted lanes are adjacent.

The number of adjacent lines must be a power

of 2. The specified bytes must be aligned on an

address boundary for the size of the data. For

example, the following values are legal for a 32-

bit slave:

• 1111 writes full 32 bits

• 0011 writes lower 2 bytes

• 1100 writes upper 2 bytes

• 0001 writes byte 0 only

• 0010 writes byte 1 only

• 0100 writes byte 2 only

• 1000 writes byte 3 only

-end

My Avalon interface is 256-bits wide (32 byte enables) and I was looking for the rules on how to use them correctly.

Thanks for replying,

Tim