For the life of me, I cannot find the document that describes byte-write limitations in Arria 10 DDR3 hard ip emif. I'm looking for the table that describes how the DM lines can and cannot be grouped in a x64 interface. Thank you.

Hi Sir,

Unfortunately, we don’t have the descriptions about byte-write limitations in Arria 10 DDR3 IP and I apologize for the inconvenience caused.

In general, one data mask (DM) pin exists per DQS group. Below is the example for x8 DDR3 interface.

So, for x64 interface, you will have total of 8 DM pins/bits. DM needs to be a differential pin-pair with a DQ pin due to the FPGA architecture. This pinout requirement is documented in the EMIF pinout guidelines. In the EMIF Handbook Volume 2, chapter 1.2.1 on page 40, it states :

"13.Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/O pin and another in the pairing pin for that I/O pin. It is recommended—though not required—that you follow the same rule for DBI pins, so that at a later date you have the freedom to repurpose the pin as DM." => https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan.pdf

I sincerely hope this helps.

Thanks

Regards,

NAli1