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Altera_Forum
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17 years ago

Floating Point Multiplier latency???

Hello, i have instantiated and synthesized an ALTFP_MULT in QuartusII with double precision and 5 output latency. I have extracted the post-synthesis netlist and successfully simulated ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Thank you Rysc! My problem was that I was misinterpreting the term output latency.

In fact it was the clock periods that I have been counting and not the edges that actually triger the registers.

So, for this design the combinational stages are 4, and the registers are 5. It takes 5 clock ticks to get a result.

Thanks for your time, +1 rep from me