Floating Point Multiplier latency???

Looks like 5 clock cyles to me. Just counting the rising edges in your simulation, I see 5. The output comes out exactly in line with the 5th rising edge because you're doing an RTL simulation, but in essence think that it occurs "after" that edge, as nothing can use it until the next rising edge. So it occurs through 5 edges(imagine 5 registers in a row), and each register sends its data out immediately. If you go to a timing simulation(which I generally don't recommend), the data will come out some finite time after this edge.