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Is latency really a factor? whats the application for this?
FPGAs really dont like doing floating point. I would reocmmened trying to convert it to fixed point as it Hugely reduces the latency and logic requirements. If you really have to do it floating point, you're stuck with long latency and large resource requirements.
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I want to first see if this can be done in floating point before looking at fixed point.
The result needs to be available every 6 us. This includes the time to load the matrice - at least the smaller one. The bigger one does not change frequently.
Yes, I want to do it with the least amount of resources.
I am targeting a Stratix 3 so if I do 56 multiplications in parallel then wil use up 224/288 ~80% of the multipliers just for this.
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