Forum Discussion

sackettaj's avatar
sackettaj
Icon for New Contributor rankNew Contributor
2 years ago

"Floating point functions Intel FPGA IP" Division configuration produces wrong answers

So I'm trying to use the "floating point functions Intel FPGA IP" library to run floating point division calculations. This library can be found in quartus prime pro edition under:

ip catalog -> installed ip -> library -> basic functions -> arithmetic -> floating point functions intel FPGA IP

I'm running into a problem where the floating point division computations are wrong. It seems like the numbers are being rounded to powers of two. Like the exponent is being computed, but not the mantissa.

Here are screenshots of my setup, along with screenshots of a questa simulation of the results.

IP SetupIP settings from the IP planner

Project + Testbench code Project navigator and test bench.

The comment on line 32 is wrong, that a value is 300 in 32 bit float, according to questa and https://www.h-schmidt.net/FloatConverter/IEEE754.html

Result

Questa Result.

a,b,q are in [radix-> "1 float 32"] format.

Worth noting, letting the simulation run for another 1000 ns doesn't help, the final value sits at that 4.0 value seemingly indefinitely.

More inputs/outputs

a = 8.0, b = 2.0 -> q = 4.0

a = 325.162, b = 12.51 -> q = 16.0

a = 120.0 b = 150.0 -> q = 1.0

a = -25 b = 8100.16 -> q = -0.00195313 = 0xbb000000

What's going on here? Am I using the IP core incorrectly? Any help would be appreciated.

4 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hello,
    the Stratix III altfp_div design example doesn't help because it's using legacy altfp IP rather than HLS based "Floating Point Functions Intel FPGA IP" available in recent Quartus versions.

    The float divider is working correctly for me. You didn't however report the device family and performance settings used in your design.
    Looks like latency of 20. Notice that the divider probably won't run at 500 MHz with this setting in real hardware, expect that the simulator doesn't care about timing violations.

    I was however simulating synthesized IP instead of sim package, synthesized with latency 15 to run at 100 MHz on Arria 10. If there's an issue with the simulation package, I won't get aware of.

    Best regards
    Frank

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    Can you please share your project to look into this issue.


    Thank you

    Kshitij Goel


  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Thank you

    Kshitij Goel