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sackettaj's avatar
sackettaj
Icon for New Contributor rankNew Contributor
2 years ago

"Floating point functions Intel FPGA IP" Division configuration produces wrong answers

So I'm trying to use the "floating point functions Intel FPGA IP" library to run floating point division calculations. This library can be found in quartus prime pro edition under: ip catalog -> in...
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hello,
the Stratix III altfp_div design example doesn't help because it's using legacy altfp IP rather than HLS based "Floating Point Functions Intel FPGA IP" available in recent Quartus versions.

The float divider is working correctly for me. You didn't however report the device family and performance settings used in your design.
Looks like latency of 20. Notice that the divider probably won't run at 500 MHz with this setting in real hardware, expect that the simulator doesn't care about timing violations.

I was however simulating synthesized IP instead of sim package, synthesized with latency 15 to run at 100 MHz on Arria 10. If there's an issue with the simulation package, I won't get aware of.

Best regards
Frank