Hi @hcom,
Coping from A10 EMIF handbook
I/O Banks Selection
• For each memory interface, select consecutive I/O banks.
• A memory interface can only span across I/O banks in the same I/O column.
• Because I/O bank 2A is also employed for configuration-related operations, you
can use it to construct external memory interfaces only when the following
conditions are met:
— The pins required for configuration related use (such as configuration bus for
Fast Passive Parallel mode or control signals for Partial Reconfiguration) are
never shared with pins selected for EMIF use, even after configuration is
complete.
— The I/O voltages are compatible.
— The design has achieved a successful fit in the Intel Quartus Prime software.
Refer to the Intel Arria 10 Device Handbook and the Configuration Function
column of the Pin-Out files for more information about pins and configuration
modes.
• The number of I/O banks that you require depends on the memory interface
width.
• The 3V I/O bank does not support dynamic OCT or calibrated OCT. To place a
memory interface in a 3V I/O bank, ensure that calibrated OCT is disabled for the
address/command signals, the memory clock signals, and the data bus signals,
during IP generation.
• In some device packages, the number of I/O pins in some LVDS I/O banks is less
that 48 pins.
Changing the termination will allow you to place in the 3V I/O bank.
I'm not able to do it in your design as the changes in the IP need to be regenerate and the top level file has missing port.
Then I create the example design by following your IP configuration.
The change is working from my side.
You may test the design that I've attached.
Thank you.
Adzim
Occasional Contributor
