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hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
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Fitter was unable to place an EMIF with a differential clock

I can see from this thread that a differential (LVDS) EMIF PLL reference clock is only supported in LVDS I/O banks (and not 3 V I/O banks) in Arria 10: https://community.intel.com/t5/Programmable-De...
  • hcom's avatar
    hcom
    4 years ago

    @AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.

    Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.

hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

@sstrell Thank you - there were 2 key features I missed:

  1. This mysterious button lists all legal placement options for a pin: .
  2. This button places all pins that only have 1 legal location remaining: .

This allowed me to confirm quite quickly that Quartus forbids the use of Bank 2L in a DDR3 interface that uses an LVDS PLL reference clock. It's not automatic by any means, but by process of elimination I was able to find that all "legal" locations turned out to be illegal.

It's a shame this doesn't appear to be documented anywhere, as I would be interested to know why this is forbidden.