Forum Discussion
Occasional ContributorFitter was unable to place an EMIF with a differential clock
@AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.
Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.
Super ContributorAre you using Standard or Pro? If you're using Pro, you could try using Interface Planner.
Also, what happens if you remove the pin assignments for the memory from the Pin Planner and just let the Fitter try a placement? You could still make a single assignment, like for CK0, to select the address/command bank, an assignment for the reference clock, one for RZQ, and each of the DQS signals. The Fitter could then select valid locations for the DQ. Use the Read Me from the IP generation as a guide.
hcom@sstrell I am using Quartus 21.3 Pro. I tried using the Interface Planner for a couple of hours, but I couldn't really see how to use the tool effectively. In the end, it just seemed easier to edit pin assignments in the Pin Planner, then compile the design. Did I miss a useful feature of the Interface Planner?
I tried many variations of constraining different pin assignments. With no pin assignments at all, the design builds without error. My key requirement is that I would like data pins to be in Bank 2L, but any attempt to do that causes an error. Actually, the differential clock could be a red herring - I'm now seeing that this constraint alone causes the fitter to fail:So maybe it is simply the case that the EMIF's data bank must be an LVDS I/O bank? I didn't find any suggestion of this in the documentation.
I will try the combinations of pin assignments you suggested, but I feel quite sure I already tried something very similar without success.
