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anonimcs's avatar
anonimcs
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2 years ago

Fitter error regarding the EMIF IP

Hi all, I have a design on Quartus Prime Standard version 17.1. (I'm already considering an upgrade to 21.3 Pro after fixing this error, so please don't recommend this straightaway). In the design t...
Memory
sstrell's avatar
sstrell
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2 years ago

What device is this? What does your Platform Designer system look like? EMIF parameterization? HPS setup for EMIF?

More detail needed here.

anonimcs's avatar
anonimcs
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2 years ago

Sorry for the lack of information.

  • The target device is an Arria 10.
  • The system can be described as: The system has 2 EMIF IPs, one for HPS and one for the FPGA fabric (the entities use the external memory for de-interleaving huge amounts of data). The HPS is used for setting some registers from a GUI, so the HPS is talking to an AXI to Avalon MM Bridge and that bridge reads/writes registers of the other entities in the fabric.
  • EMIF parameterization: 1200 MHz memory clock, with HPS Early Release. HPS EMIF uses half clock rate of user logic, fabric uses Quarter. Not sure what else you'd like to learn here since there are quite a lot of parameters.