Forum Discussion
Nathan_R_Intel
Contributor
7 years agoHie Sunil,
Yes this seems related to transceiver location constraints. Please check if you are following the PCIe channel placement guideline as described in Section 4.4. in Arria 10 PCIe user guide. The link to user guide is below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf
Regards,
Nathan