Forum Discussion
The filter itself uses an active low reset and the coefficient reload interface uses an asynchronous active high reset. Don't ask me why. In practice, the coeff_in_areset doesn't appear to do anything (at least in my configuration). Writing a new coefficient appears to take effect immediately.
Using a 16-bit or less coefficient width will configure the FIR for a 16-bit coefficient data port. Using a 17-bit or larger coefficient width will configure the FIR for a 32-bit coefficient data port.
The two pictures from SignalTap appear to show identical operation for the two different coefficient addresses. Can you point out the difference?
Make sure your HPS addressing is being handled properly. You need to read coefficient addresses 0, 1, 2, 3, 4, 5, etc. Don't jump by 4 when using a 32-bit HPS bus. Be aware that you only need to write and read-back half of the coefficients for a symmetrical FIR filter. If you have an odd number of coefficients, write and read one additional address. For example, if you have 41 coefficients, you'll need to write to the first 21 addresses in the FIR filter to reprogram them all.
What clock do you have connected to the coeff_in_clk port?